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19-0892; Rev 3; 12/96
CMOS High-Speed 8-Bit ADCs with Multiplexer and Reference
_______________General Description
The MAX154/MAX158 are high-speed multi-channel analog-to-digital converters (ADCs). The MAX154 has four analog input channels while the MAX158 has eight channels. Conversion time for both devices is 2.5s. The MAX154/MAX158 also feature a 2.5V on-chip reference, forming a complete high-speed data acquisition system. Both converters include a built-in track/hold, eliminating the need for an external track/hold. The analog input range is 0V to +5V, although the ADC operates from a single +5V supply. Microprocessor interfaces are simplified by the ADC's ability to appear as a memory location or I/O port without the need for external logic. The data outputs use latched, three-state buffer circuitry to allow direct connection to a microprocessor data bus or system input port.
____________________________Features
o One-Chip Data Acquisition System o Four or Eight Analog Input Channels o 2.5s per Channel Conversion Time o Internal 2.5V Reference o Built-In Track/Hold Function o 1/2LSB Error Specification o Single +5V Supply Operation o No External Clock o New Space-Saving SSOP Package
MAX154/MAX158
______________Ordering Information
PART MAX154ACNG TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C PIN-PACKAGE 24 Narrow Plastic DIP 24 Narrow Plastic DIP Dice 24 Wide SO 24 Wide SO 24 SSOP 24 SSOP ERROR (LSB) 1/2 1 1/2 1/2 1 1/2 1
________________________Applications
Digital Signal Processing High-Speed Data Acquisition Telecommunications High-Speed Servo Control Audio Instrumentation
MAX154BCNG MAX154BC/D MAX154ACWG MAX154BCWG MAX154ACAG MAX154BCAG
Ordering Information continued at end of data sheet.
__________________________________________________________Pin Configurations
TOP VIEW
AIN6 1 AIN4 1 AIN3 2 AIN2 3 AIN1 4 REF OUT 5 DB0 6 DB1 7 DB2 8 DB3 9 RD 10 INT 11 GND 12 24 VDD 23 N.C. 22 A0 21 A1 AIN5 2 AIN4 3 AIN3 4 AIN2 5 AIN1 6 REF OUT 7 DB0 8 DB1 9 DB2 10 DB3 11 RD 12 INT 13 GND 14 28 AIN7 27 AIN8 26 VDD 25 A0
MAX158
24 A1 23 A2 22 DB7 21 DB6 20 DB5 19 DB4 18 CS 17 RDY 16 VREF+ 15 VREF-
MAX154
20 DB7 19 DB6 18 DB5 17 DB4 16 CS 15 RDY 14 VREF+ 13 VREF-
DIP/SO/SSOP DIP/SO/SSOP
________________________________________________________________ Maxim Integrated Products
1
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CMOS High-Speed 8-Bit ADCs with Multiplexer and Reference MAX154/MAX158
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD to GND.........................................0V, +10V Voltage at Any Other Pins........................GND -0.3V, VDD +0.3V Output Current (REF OUT)..................................................30mA Power Dissipation (any package) to +75C ....................450mW Derate above +25C by ..............................................6mW/C Operating Temperature Ranges MAX15_ _C_ _.....................................................0C to +70C MAX15_ _E_ _ ..................................................-40C to +85C MAX15_ _M_ _ ...............................................-55C to +125C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V, VREF+ = +5V, VREF- = GND, Mode 0, TA = TMIN to TMAX, unless otherwise noted). PARAMETER ACCURACY Resolution Total Unadjusted Error (Note 1) No-Missing-Codes Resolution Channel-to-Channel Mismatch REFERENCE INPUT Reference Resistance VREF+ Input Voltage Range VREF- Input Voltage Range REFERENCE OUTPUT (Note 2) Output Voltage Load Regulation Power-Supply Sensitivity Temperature Drift (Note 3) Output Noise Capacitive Load ANALOG INPUT Analog Input Voltage Range Analog Input Capacitance Analog Input Current AINR CAIN IAIN Any channel, AIN = 0V to 5V 0.7 2.4 0.8 1 -1 5 8 VREF45 3 0.157 VREF+ V pF A V/s V V A A pF eN REF OUT TA = +25C IL = 0mA to 10mA, TA = +25C VDD 5%, TA = +25C MAX15_ _C MAX15_ _E MAX15_ _M 2.47 2.50 -6 1 40 40 60 200 0.01 2.53 -10 3 70 70 100 V/rms F ppm/C V mV mV 1 VREFGND 4 VDD VREF+ k V V MAX15_A MAX15_B 8 1/4 8 1/2 1 Bits LSB Bits LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
Slew Rate, Tracking SR -- -- ---- LOGIC INPUTS ( RD , CS , A0, A1, A2) Input High Voltage Input Low Voltage Input High Current Input Low Current Input Capacitance (Note 4) VINH VINL IINH IINL CIN
2
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CMOS High-Speed 8-Bit ADCs with Multiplexer and Reference
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V, VREF+ = +5V, VREF- = GND, MODE 0, TA = TMIN to TMAX, unless otherwise noted). PARAMETER LOGIC OUTPUTS Output High Voltage Output Low Voltage Three-State Output Current Output Capacitance (Note 4) POWER-SUPPLY Supply Voltage Supply Current Power Dissipation Power-Supply Sensitivity Note 1: Note 2: Note 3: Note 4: PSS VDD = 5% VDD IDD 5V 5% for specified performance CS = RD = 2.4V 25 1/16 4.75 5.25 15 75 1/4 V mA mW LSB COUT VOH VOL DB0-DB7, INT; IOUT = -360A DB0-DB7, INT; RDY IOUT = 1.6mA IOUT = 2.6mA 5 4.0 0.4 0.4 3 8 V V A pF SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX154/MAX158
DB0-DB7, RDY; VOUT = 0V to VDD
Total unadjusted error includes offset, full-scale, and linearity errors. Specified with no external load unless otherwise noted. Temperature drift is defined as change in output voltage from +25C to TMIN or TMAX divided by (25 - TMIN) or (TMAX - 25). Guaranteed by design.
TIMING CHARACTERISTICS (Note 5)
(VDD = +5V, VREF+ = +5V, VREF- = GND, MODE 0, TA = TMIN to TMAX, unless otherwise noted). TA = +25C MIN CS to RD Setup Time CS to RD Hold Time Multiplexer Address Setup Time Multiplexer Address Hold Time CS to RDY Delay Conversion Time (Mode 0) Data Access Time After RD Data Access Time After INT, Mode 0 RD to INT Delay (Mode 1) Data Hold Time Delay Time Between Conversions RD Pulse Width (Mode 1) tCSS tCSH tAS tAH tRDY tCRD tACC1 tACC2 tINTH tDH tP tRD (Note 6) (Note 6) CL = 50pF (Note 7) 500 60 600 20 40 CL = 50pF, RL = 5k 0 0 0 30 30 1.6 40 2.0 85 50 75 60 500 80 500 TYP MAX MAX15_C/E MIN 0 0 0 35 60 2.4 110 60 100 70 600 80 400 MAX MAX15_M MIN 0 0 0 40 60 2.8 120 70 100 70 MAX ns ns ns ns ns s ns ns ns ns ns ns
PARAMETER
SYMBOL
CONDITIONS
UNITS
Note 5: All input control signals are specified with tR = tF = 20ns (10% to 90% of +5V) and timed from a 1.6V voltage level. Note 6: Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V. Note 7: Defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
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3
CMOS High-Speed 8-Bit ADCs with Multiplexer and Reference MAX154/MAX158
__________________________________________Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
REFERENCE TEMPERATURE DRIFT
MX7824/28-1
OUTPUT CURRENT vs. TEMPERATURE
MX7824/28-2
ACCURACY vs. DELAY BETWEEN CONVERSIONS (tp)
VDD = 5V VREF = 5V 1.5
MX7824/28-3
2.520
20 VDD = 5V OUTPUT CURRENT (mA) 16 ISOURCE VOUT = 2.4V 12
2.0
REF OUT VOLTAGE (V)
2.510
LINEARITY ERROR (LSB) 150
2.500
1.0
8 ISINK VOUT = 0.4V 4
2.490
0.5
2.480 -50 0 50 100 150 AMBIENT TEMPERATURE (C)
0 -100 -50 0 50 100 AMBIENT TEMPERATURE (C)
0 300 400 500 600 tp (ns) 700 800 900
ACCURACY vs. VREF [VREF = VREF(+) - VREF(-)]
MX7824/28-4
POWER-SUPPLY CURRENT vs. TEMPERATURE (NOT INCLUDING REFERENCE LADDER)
MX7824/28-5
2.0 VDD = 5V LINEARITY ERROR (LSB) 1.5
8 IDD - SUPPLY CURRENT (mA) 7 6 5 4 3 2 VDD = 4.75V VDD = 5.25V
1.0
VDD = 5V
0.5
0 0 1 2 3 4 5 VREF (V)
-100
-50
0
50
100
150
AMBIENT TEMPERATURE (C)
+5V 3k DBN 3k DGND 100pF DBN 10pF DGND DBN 3k DGND 100pF DBN
+5V 3k
10pF DGND
a. High-Z to VOH
b. High-Z to VOL
a. High-Z to VOH
b. High-Z to VOL
Figure 1. Load Circuits for Data-Access Time Test
4
Figure 2. Load Circuits for Data-Hold Time Test
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CMOS High-Speed 8-Bit ADCs with Multiplexer and Reference
_____________________________________________________________Pin Descriptions
PIN MAX154 1 2 3 4 5 6 7 8 9 10 NAME AIN4 AIN3 AIN2 AIN1 REF OUT DBO DB1 DB2 DB3 RD FUNCTION Analog Input Channel 4 Analog Input Channel 3 Analog Input Channel 2 Analog Input Channel 1 Reference Output (2.5V) for MAX154 Three-State Data Output, bit 0 (LSB) Three-State Data Output, bit 1 Three-State Data Output, bit 2 Three-State Data Output, bit 3 Read Input. RD controls conversions and data access. See Digital Interface section. Interrupt Output. INT going low indicates the completion of a conversion. See Digital Interface section. Ground Lower Limit of Reference Span. Sets the zero-code voltage. Range: GND to VREF+. Upper Limit of Reference Span. Sets the full-scale input voltage. Range: VREF- to VDD. Ready Output. Open-drain output with no active pull-up device. Goes low when CS goes low and high impedance at the end of a conversion. Chip-Select Input. CS must be low for the device to be selected. Three-State Data Output, bit 4 Three-State Data Output, bit 5 Three-State Data Output, bit 6 Three-State Data Output, bit 7 (MSB) Channel Address 1 Input Channel Address 0 Input No Connect Power-Supply Voltage, +5V PIN MAX158 1 2 3 4 5 6 7 8 9 10 11 12 NAME AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 REF OUT DB0 DB1 DB2 DB3 RD FUNCTION Analog Input Channel 6 Analog Input Channel 5 Analog Input Channel 4 Analog Input Channel 3 Analog Input Channel 2 Analog Input Channel 1 Reference Output (2.5V) for MAX158 Three-State Data Output, bit 0 (LSB) Three-State Data Output, bit 1 Three-State Data Output, bit 2 Three-State Data Output, bit 3 Read Input. RD controls conversions and data access. See Digital Interface section. Interrupt Output. INT going low indicates the completion of a conversion. See Digital Interface section. Ground Lower Limit of Reference Span. Sets the zero-code voltage. Range: GND to VREF+. Upper Limit of Reference Span. Sets the full-scale input voltage. Range: VREF- to VDD. Ready Output. Open-drain output with no active pull-up device. Goes low when CS goes low and high impedance at the end of a conversion. - Chip-Select input. CS must be low for the device to be selected. Three-State Data Output, bit 4 Three-State Data Output, bit 5 Three-State Data Output, bit 6 Three-State Data Output, bit 7 (MSB) Channel Address 2 Input Channel Address 1 Input Channel Address 0 Input Power-Supply Voltage, +5V Analog Input Channel 8 Analog Input Channel 7 5
MAX154/MAX158
11 12 13
INT GND VREF-
13 14 15
INT GND VREF-
14
VREF+
16
VREF+
15
RDY
17
RDY
16 17 18 19 20 21 22 23 24
CS DB4 DB5 DB6 DB7 A1 A0 NC VDD
18 19 20 21 22 23 24 25 26 27 28
CS DB4 DB5 DB6 DB7 A2 A1 A0 VDD AIN8 AIN7
_______________________________________________________________________________________
CMOS High-Speed 8-Bit ADCs with Multiplexer and Reference MAX154/MAX158
_______________Detailed Description
Converter Operations
The MAX154/MAX158 use what is commonly called a "half-flash" conversion technique (Figure 3). Two 4-bit flash ADC converter sections are used to achieve an 8bit result. Using 15 comparators, the upper 4-bit MS (most significant) flash ADC compares the unknown input voltage to the reference ladder and provides the upper four data bits. An internal DAC uses the MS bits to generate an analog signal from the first flash conversion. A residue voltage representing the difference between the unknown input and the DAC voltage is then compared to the reference ladder by 15 LS (least significant) flash comparators to obtain the lower four output bits.
___________________Digital Interface
The MAX154/MAX158 use only Chip Select (CS) and Read (RD) as control inputs. A READ operation, taking CS and RD low, latches the multiplexer address inputs and starts a conversion (Table 1).
Table 1. Truth Table for Input Channel Selection
MAX154/MX7824 A1 A0 0 0 0 1 1 0 1 1 MAX158/MX7828 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 SELECTED CHANNEL AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8
Operating Sequence
The operating sequence is shown in Figure 4. A conversion is initiated by a falling edge of RD and CS. The comparator inputs track the analog input voltage for approximately 1s. After this first cycle, the MS flash result is latched into the output buffers and the LS conversion begins. INT goes low approximately 600ns later, indicating the end of the conversion, and that the lower four bits are latched into the output buffers. The data can then be accessed using the CS and RD inputs.
There are two interface modes, which are determined by the length of the RD input. Mode 0, implemented by keeping RD low until the conversion ends, is designed for microprocessors that can be forced into a WAIT state. In this mode, a conversion is started with a READ operation (taking CS and RD low), and data is read when the conversion ends. Mode 1, on the other hand, does not require microprocessor WAIT states. A READ operation simultaneously initiates a conversion and reads the previous conversion result.
VREF+ VREFAIN1
4-BIT FLASH ADC (4MSB)
DB7 DB6 DB5 DB4
AIN4
MUX*
4-BIT DAC
THREESTATE DRIVERS
AIN8
VREF+ 16
4-BIT FLASH ADC (4LSB)
DB3 DB2 DB1 DB0 TIMING AND CONTROL CIRCUITRY
REF OUT
2.5V REF
ADDRESS LATCH DECODE A0 A1 A2 RDY
INT
*MAX154 - 4-Channel Mux MAX158 - 8-Channel Mux
CS
RD
Figure 3. Functional Diagram
6 _______________________________________________________________________________________
CMOS High-Speed 8-Bit ADCs with Multiplexer and Reference
RD 500ns 1000ns 600ns INT GOING LOW INDICATES THAT CONVERSION IS COMPLETE AND THAT DATA CAN BE READ
SETUP TIME REQUIRED BY THE INTERNAL COMPARATORS PRIOR TO STARTING CONVERSION
VIN IS SAMPLED AND THE FOUR MSBs ARE LATCHED
device), is connected to the processor's READY/WAIT input. RDY goes low on the falling edge of CS and goes high impedance at the end of the conversion, when the conversion result appears on the data outputs. If the RDY output is not required, its external pull-up resistor can be omitted. INT goes low when the conversion is complete and returns high on the rising edge of CS or RD.
MAX154/MAX158
VIN IS TRACKED BY INTERNAL COMPARATORS
Interface Mode 1
Mode 1 is designed for applications where the microprocessor is not forced into a WAIT state. Taking CS and RD low latches the multiplexer address and starts a conversion (Figure 6). Data from the previous conversion is immediately read from the outputs (DB0-DB7). INT goes high at the rising edge of CS or RD and goes low at the end of the conversion. A second READ operation is required to read the result of this conversion. The second READ latches a new multiplexer address and starts another conversion. A delay of 2.5s must be allowed between READ operations. RDY goes low on the falling edge of CS and goes high impedance at the rising edge of CS. If RDY is not needed, its external pull-up resistor can be omitted.
Figure 4. Operating Sequence
Interface Mode 0
Figure 5 shows the timing diagram for Mode 0 operation. This is used with microprocessors that have WAIT state capability, whereby a READ instruction is extended to accommodate slow-memory devices. Taking CS and RD low latches the analog multiplexer address and starts a conversion. Data outputs DB0-DB7 remain in the high-impedance condition until the conversion is complete. There are two status outputs: Interrupt (INT) and Ready (RDY). RDY, an open-drain output (no internal pull-up
CS
tCSS RD
tCSH
tCSS
tP tAS ANALOG CHANNEL ADDRESS RDY tRDY ADDR VALID tAH tAS ADDR VALID
INT
tINTH tCRD tACC2 tDH DATA VALID
DATA
HIGH IMPEDANCE
Figure 5. Mode 0 Timing Diagram
_______________________________________________________________________________________
7
CMOS High-Speed 8-Bit ADCs with Multiplexer and Reference MAX154/MAX158
CS
tCSS RD
tRD
tCSH
tCSS
tRD
tCSH
tP tAS ANALOG CHANNEL ADDRESS RDY tRDY tCRD tINTH tINTH tRDY ADDR VALID tAH tAS ADDR VALID tAH
INT
tACCI OLD DATA
tDH
tACCI NEW DATA
tDH
DATA
Figure 6. Mode 1 Timing Diagram
_____________Analog Considerations
Reference and Input
The VREF+ and VREF- inputs of the converter define the zero and the full-scale of the ADC. In other words, the voltage at VREF- is equal to the input voltage that produces an output code of all zeros, and the voltage at VREF+ is equal to input voltage that produces an output code of all ones (Figure 7). Figure 8 shows some possible reference configurations. A 0.01F bypass capacitor to GND should be used to reduce the high-frequency output impedance of the internal reference. Larger capacitors should not be used, as this degrades the stability of the reference buffer. The 2.5V reference output is with respect to the GND pin.
OUTPUT CODE 11111111 11111110 11111101 FULL-SCALE TRANSITION
1LSB = F8 = VREF+ - VREF256 256 00000011 00000010 00000001 00000000 VREF1 2 3 AIN INPUT VOLTAGE (IN TERMS OF LSBs) FS-1LSB FS VREF+
Bypassing
A 47F electrolytic and 0.1F ceramic capacitor should be used to bypass the VDD pin to GND. These capacitors must have minimum lead length, since excess lead length may contribute to conversion errors and instability. If the reference inputs are driven by long lines, they should be bypassed to GND with 0.1F capacitors at the reference input pins.
8
Figure 7. Transfer Function
_______________________________________________________________________________________
CMOS High-Speed 8-Bit ADCs with Multiplexer and Reference
Input Current
AINx(+) AINx(-) VIN GND
MAX154/MAX158
+5V
VDD REFOUT
MAX154 MAX158
0.1F
47F VREF+ 0.01F VREF-
Figure 8a. Internal Reference
AINx(+) AINx(-)
VIN GND
+5V 0.1F 47F
VDD VREF+ VREF-
MAX154 MAX158
The converters' analog inputs behave somewhat differently from conventional ADCs. The sampled data comparators take varying amounts of current from the input, depending on the cycle they are in. The equivalent circuit of the converter is shown in Figure 9a. When the conversion starts, AIN(n) is connected to the MS and LS comparators. Thus, AIN(n) is connected to thirty-one 1pF capacitors. To acquire the input signal in approximately 1s, the input capacitors must charge to the input voltage through the on-resistance of the multiplexer (about 600) and the comparator's analog switches (2k to 5k per comparator). In addition, about 12pF of stray capacitance must be charged. The input can be modeled as an equivalent RC network shown in Figure 9b. As RS (source impedance) increases, the capacitors take longer to charge. Since the length of the input acquisition time is internally set, large source resistances (greater than 100) will cause settling errors. The output impedance of an opamp is its open-loop output impedance divided by the loop gain at the frequency of interest. It is important that the amplifier driving the converter input have sufficient loop gain at approximately 1MHz to maintain low output impedance.
Input Filtering
The transients in the analog input caused by the sampled data comparators do not degrade the converter's performance, since the ADC does not "look" at the input when these transients occur. The comparator's outputs track the input during the first 1s of the conversion, and are then latched. Therefore, at least 1s will be provided to charge the ADC's input capacitance. It is not necessary to filter these transients with an external capacitor on the AIN terminals.
Figure 8b. Power Supply as Reference
* Current path must still exist from VIN(-) to Ground
Sinusoidal Inputs
AINx(+) VIN GND
+5V 0.1F 47F 2.5V AINx(-) *
VDD VREF+
MAX154 MAX158
VREF-
The MAX154/MAX158 can measure input signals with slew rates as high as 157mV/s to the rated specifications. This means that the analog input frequency can be as high as 10kHz without the aid of an external track/hold. The maximum sampling rate is limited by the conversion time (typical tCRD = 2s) plus the time required between conversions (tp = 500ns). It is calculated as: fMAX = 1 1 = = 400kHz tCRD + tp (2.0 + 0.5) s fMAX permits a maximum sampling rate of 50kHz per channel when using the MAX158 and 100kHz per channel when using the MAX154. These rates are well above the Nyquist requirement of 20kHz sampling rate for a 10kHz input bandwidth.
9
Figure 8c. Inputs Not Referenced to GND
_______________________________________________________________________________________
CMOS High-Speed 8-Bit ADCs with Multiplexer and Reference MAX154/MAX158
Bipolar Input Operation
The circuit in Figure 10a can be used for bipolar input operation. The input voltage is scaled by an amplifier so that only positive voltages appear at the ADC's inputs. The analog input range is 4V and the output code is complementary offset binary. The ideal input/output characteristic is shown in Figure 10b.
CS 2pF RON 1pF 1pF * TO LS * LADDER * 15 LSB COMPARATORS
11111111 11111110 11111101 10000010 10000001 10000000 01111111 01111110 00000010 00000001 00000000 -FS + 1LSB 2
FS = 8V 1LSB = FS / 256
RS VIN
AIN1
RMUX
+FS 2
CS 12pF
RON 1pF 1pF * TO MS * LADDER * 16 MSB COMPARATORS 0V AIN INPUT VOLTAGE (LSBs)
Figure 9a. Equivalent Input Circuit
RS VIN B MUX 600 CS1 2pF RON 350 CS2 2pF 32pF
Figure 10b. Transfer Function for 4V Input Operation
AIN1
A15 ADDRESS BUS A0
Figure 9b. RC Network Model
3.57k VIN 11.5 ZBO 10.0k AIN1 CS MREQ 5V 5k WAIT RD D0-D7 DATA BUS CS RDY RD DB0-DB7 EN ADDRESS DECODE A0 A1 A2*
MAX154 MAX158
0.01F
16.2k
MAX154 MAX158
RDY RD
0.01F
VREF+ REFOUT
INT
+5V
VDD VREF47F
DB0-DB7 *A2 ON MAX158.
0.1F
GND
ONLY CHANNEL 1 SHOWN
Figure 11. Simple Mode 0 Interface
Figure 10a. Bipolar 4V Input Operation
10 ______________________________________________________________________________________
CMOS High-Speed 8-Bit ADCs with Multiplexer and Reference
_Ordering Information (continued)
+5V 26 VDD BANDPASS FILTER 1 BANDPASS FILTER 2 6 AIN1 CS RD 5 AIN2 18 12
MAX154/MAX158
PART
TEMP. RANGE
PIN-PACKAGE 24 Plastic DIP 24 Plastic DIP 24 Wide SO 24 Wide SO 24 SSOP 24 SSOP 24 CERDIP 24 CERDIP 28 Plastic DIP 28 Plastic DIP Dice 28 Wide SO 28 Wide SO 28 SSOP 28 SSOP 28 Plastic DIP 28 Plastic DIP 28 Wide SO 28 Wide SO 28 SSOP 28 SSOP 28 CERDIP 28 CERDIP
ERROR (LSB) 1/2 1 1/2 1 1/2 1 1/2 1 1/2 1 1/2 1/2 1 1/2 1 1/2 1 1/2 1 1/2 1 1/2 1
MAX154AENG -40C to +85C MAX154BENG -40C to +85C MAX154AEWG -40C to +85C MAX154BEWG -40C to +85C MAX154AEAG -40C to +85C MAX154BEAG -40C to +85C
DATA
MAX158
SPEECH INPUT AMP DB0-DB7 BANDPASS FILTER 7 BANDPASS FILTER 8 +5V 28
AIN7 A2 23 24 25
MAX154AMRG -55C to +125C MAX154BMRG -55C to +125C MAX158ACPI 0C to +70C 0C to +70C MAX158BCPI MAX158BC/D 0C to +70C MAX158ACWI MAX158BCWI MAX158ACAI MAX158BCAI MAX158AEPI MAX158BEPI MAX158AEWI MAX158BEWI MAX158AEAI MAX158BEAI MAX158AMJI MAX158BMJI 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C
27 AIN8 16 VREF+ VREF15
A1 A0 GND 14
Figure 12. Speech Analysis Using Real-Time Filtering
+5V 24 VDD 4 AIN1 3 AIN2 2 AIN3 1 AIN4 14 V REF+ 13 12 VREFGND A0 A1 A1 21 A0 22 16 CS 10 RD
SAMPLE PULSE
+5V 18 VDD VREF 4 WR VOUT A 2 +5V
INT 11
15
MAX154
DB0-DB7 16 17
MAX506
DB0-DB7
VOUT B 1 VOUT C VOUT D 20 19 6
A1 A0 VSS 3
DGND
AGND 5
Figure 13. 4-Channel Fast Sample and Infinite Hold
______________________________________________________________________________________ 11
CMOS High-Speed 8-Bit ADCs with Multiplexer and Reference MAX154/MAX158
___________________Chip Topography
AIN4 AIN6 AIN8 (N.C.) (AIN2) (AIN4) AIN3 AIN5 AIN7 (N.C.) (AIN1) (AIN3)
VDD A0
AIN2 (N.C.) AIN1 (N.C.) TP (REF OUT) DB0
A1 A2 (N.C.) 0.127" (3.228mm) DB7 DB6
DB1 DB5 DB2 DB4 DB3 CS A0 GND VREF+ INT VREF0.124" (3.150mm) ADY
________________________________________________________Package Information
DIM A A1 B C D E e H L INCHES MILLIMETERS MIN MAX MIN MAX 0.068 0.078 1.73 1.99 0.002 0.008 0.05 0.21 0.010 0.015 0.25 0.38 0.004 0.008 0.09 0.20 SEE VARIATIONS 0.205 0.209 5.20 5.38 0.0256 BSC 0.65 BSC 0.301 0.311 7.65 7.90 0.025 0.037 0.63 0.95 0 8 0 8 INCHES MILLIMETERS MAX MIN MAX MIN 6.33 0.239 0.249 6.07 6.33 0.239 0.249 6.07 7.33 0.278 0.289 7.07 8.33 0.317 0.328 8.07 0.397 0.407 10.07 10.33
21-0056A
( ) ARE FOR MAX154/MX7824
E
H
C
L
DIM PINS
e
A B D
A1
SSOP SHRINK SMALL-OUTLINE PACKAGE
D D D D D
14 16 20 24 28
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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